FIGS. 5(a) to 5(d) show process steps in a prior art method for producing a semiconductor device. As shown in FIG. 5(a), an active layer 2 is produced at a desired position in a semi-insulating GaAs substrate 1 by ion implantation.
A refractory metal 4, such as tungsten silicide (hereinafter referred to as WSi.sub.x), is deposited on the entire surface of the semi-insulating GaAs substrate 1 by sputtering or vapor deposition, and a pattern of photoresist 11 is formed where a gate is to be prepared, as shown in FIG. 5(b). As shown in FIG. 5(c), part of the WSi.sub.x 4 is removed by reactive ion etching using the photoresist 11 as a mask, thereby producing a gate electrode 4'. Finally, as shown in FIG. 5(d), ion implantation using the WSi.sub.x 4' as a mask produces high dopant concentration regions 5 (hereinafter referred to as an n.sup.+ region) after annealing, and a drain electrode 6 and a source electrode 7 are respectively produced thereon.
In the prior art method, in order to produce a gate electrode 4', patterning of the photoresist 11 is required. The precision of gate pattern depends on the precision of the photolithographic alignment technique. Furthermore, because the WSi.sub.x 4' is used as a mask for the ion implantation step, the n.sup.+ regions 5 below the source electrode 7 and the gate electrode 4' are close to each other, reducing the source resistance, advantageously increasing the gain of the FET. However, since the n.sup.+ regions 5 below the drain electrode 6 and the gate electrode 4' are close to each other, reducing the gate-drain breakdown voltage, this low gate-drain breakdown voltage makes it difficult to use this structure in high power analog ICs.